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| Features * Low-Voltage and Standard-Voltage Operation - 5.0 (VCC = 4.5V to 5.5V) - 2.7 (VCC = 2.7V to 5.5V) - 2.5 (VCC = 2.5V to 5.5V) - 1.8 (VCC = 1.8V to 5.5V) Low-Power Devices (ISB = 2=A @ 5.5V) Available Internally Organized 4096 x 8, 8192 x 8 2-Wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 100 kHz (1.8V, 2.5V, 2.7V) and 400 kHz (5V) Clock Rate Write Protect Pin for Hardware Data Protection 32-Byte Page Write Mode (Partial Page Writes Allowed) Self-Timed Write Cycle (10 ms max) High Reliability - Endurance: 1 Million Write Cycles - Data Retention: 100 Years - ESD Protection: >3,000V Automotive Grade and Extended Temperature Devices Available 8-Pin JEDEC PDIP, 8-Pin JEDEC SOIC, 8-Pin EIAJ SOIC, and 8-pin TSSOP Packages * * * * * * * * * * 2-Wire Serial EEPROM 32K (4096 x 8) 64K (8192 x 8) * * Description The AT24C32/64 provides 32,768/65,536 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device's cascadable feature allows up to 8 devices to share a common 2wire bus. The device is optimized for use in many industrial and commercial applications where low power and low voltage operation are essential. The AT24C32/64 is available in space saving 8-pin JEDEC PDIP, 8-pin JEDEC SOIC, 8-pin EIAJ SOIC, and 8-pin TSSOP (AT24C64) packages and is accessed via a 2-wire serial interface. In addition, the entire family is available in 5.0V (4.5V to 5.5V), 2.7V (2.7V to 5.5V), 2.5V (2.5V to 5.5V) and 1.8V (1.8V to 5.5V) versions. AT24C32 AT24C64 Pin Configurations Pin Name A0 - A2 SDA SCL WP Function Address Inputs Serial Data Serial Clock Input Write Protect A0 A1 A2 GND 8-Pin TSSOP 1 2 3 4 8 7 6 5 VCC WP SCL SDA 2-Wire, 32K Serial E2PROM 8-Pin PDIP A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA 8-Pin SOIC A0 A1 A2 GND 1 2 3 4 8 7 6 5 VCC WP SCL SDA Rev. 0336G-04/01 1 Absolute Maximum Ratings* Operating Temperature.................................. -55C to +125C Storage Temperature ..................................... -65C to +150C Voltage on Any Pin with Respect to Ground .....................................-1.0V to +7.0V Maximum Operating Voltage .......................................... 6.25V DC Output Current........................................................ 5.0 mA *NOTICE: Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Block Diagram Pin Description SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open collector devices. DEVICE/PAGE ADDRESSES (A2, A1, A0): The A2, A1 and A0 pins are device address inputs that are hard wired or left not connected for hardware compatibility with AT24C16. When the pins are hardwired, as many as eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). When the pins are not hardwired, the default A2, A1, and A0 are zero. WRITE PROTECT (WP): The write protect input, when tied to GND, allows normal write operations. When WP is tied high to V CC, all write operations to the upper quandrant (8/16K bits) of memory are inhibited. If left unconnected, WP is internally pulled down to GND. Memory Organization AT24C32/64, 32K/64K SERIAL EEPROM: The 32K/64K is internally organized as 256 pages of 32 bytes each. Random word addressing requires a 12/13 bit data word address. 2 AT24C32/64 AT24C32/64 Pin Capacitance(1) Applicable over recommended operating range from TA = 25C, f = 1.0 MHz, VCC = +1.8V. Symbol CI/O CIN Note: Test Condition Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, SCL) 1. This parameter is characterized and is not 100% tested. Max 8 6 Units pF pF Conditions VI/O = 0V VIN = 0V DC Characteristics Applicable over recommended operating range from: TAI = -40C to +85C, VCC = +1.8V to +5.5V, TAC = 0C to +70C, VCC = +1.8V to +5.5V (unless otherwise noted). Symbol VCC1 VCC2 VCC3 VCC4 ICC1 ICC2 ISB1 Parameter Supply Voltage Supply Voltage Supply Voltage Supply Voltage Supply Current Supply Current Standby Current (1.8V option) Standby Current (2.5V option) Standby Current (2.7V option) Standby Current (5V option) Input Leakage Current Output Leakage Current Input Low Level(1) Input High Level(1) Output Low Level Output Low Level VCC = 3.0V VCC = 1.8V IOL = 2.1 mA IOL = 0.15 mA VCC = 5.0V VCC = 5.0V VCC = 1.8V VCC = 5.5V VCC = 2.5V VCC = 5.5V VCC = 2.7V VCC = 5.5V VCC = 4.5 - 5.5V VIN = VCC or VSS VOUT = VCC or VSS -0.6 VCC x 0.7 READ at 100 kHz WRITE at 100 kHz VIN = VCC or VSS Test Condition Min 1.8 2.5 2.7 4.5 0.4 2.0 Typ Max 5.5 5.5 5.5 5.5 1.0 3.0 0.1 2.0 0.5 VIN = VCC or VSS 2.0 0.5 VIN = VCC or VSS VIN = VCC or VSS 20 0.10 0.05 2.0 35 3.0 3.0 VCC x 0.3 VCC + 0.5 0.4 0.2 A A A V V V V A A Units V V V V mA mA A ISB2 ISB3 ISB4 ILI ILO VIL VIH VOL2 VOL1 Notes: 1. VIL min and VIH max are reference only and are not tested. 3 AC Characteristics Applicable over recommended operating range from TA = -40C to +85C, VCC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted). 1.8-volt Symbol fSCL tLOW tHIGH tI tAA tBUF tHD.STA tSU.STA tHD.DAT tSU.DAT tR tF tSU.STO tDH tWR Endurance(1) Note: Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Noise Suppression Time (1) 2.7-, 2.5-volt Min Max 100 4.7 4.0 5.0-volt Min Max 400 1.2 0.6 Units kHz s s 50 0.1 1.2 0.6 0.6 0 100 0.9 ns s s s s s ns 0.3 300 0.6 50 s ns s ns 10 1M ms Write Cycles Min Max 100 4.7 4.0 100 0.1 4.7 4.0 4.7 0 200 1.0 300 4.7 100 20 1M 4.5 100 0.1 4.7 4.0 4.7 0 200 1.0 300 4.7 100 10 1M 4.5 Clock Low to Data Out Valid Time the bus must be free before a new transmission can start(1) Start Hold Time Start Set-up Time Data In Hold Time Data In Set-up Time Inputs Rise Time(1) Inputs Fall Time(1) Stop Set-up Time Data Out Hold Time Write Cycle Time 5.0V, 25C, Page Mode 1. This parameter is characterized and is not 100% tested. Device Operation CLOCK and DATA TRANSITIONS: The SDA pin is normally pulled high with an external device. Data on the SDA pin may change only during SCL low time periods (refer to Data Validity timing diagram). Data changes during SCL high periods will indicate a start or stop condition as defined below. START CONDITION: A high-to-low transition of SDA with SCL high is a start condition which must precede any other command (refer to Start and Stop Definition timing diagram). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. After a read sequence, the stop command will place the EEPROM in a standby power mode (refer to Start and Stop Definition timing diagram). ACKNOWLEDGE: All addresses and data words are serially transmitted to and from the EEPROM in 8-bit words. The EEPROM sends a zero during the ninth clock cycle to acknowledge that it has received each word. STANDBY MODE: The AT24C32/64 features a low power standby mode which is enabled: a) upon power-up and b) after the receipt of the STOP bit and the completion of any internal operations. MEMORY RESET: After an interruption in protocol, power loss or system reset, any 2-wire part can be reset by following these steps: (a) Clock up to 9 cycles, (b) look for SDA high in each cycle while SCL is high and then (c) create a start condition as SDA is high. 4 AT24C32/64 AT24C32/64 Bus Timing SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O tWR(1) Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. 5 Data Validity Start and Stop Definition Output Acknowledge 6 AT24C32/64 AT24C32/64 Device Addressing The 32K/64K EEPROM requires an 8-bit device address word following a start condition to enable the chip for a read or write operation (refer to Figure 1). The device address word consists of a mandatory one, zero sequence for the first four most significant bits as shown. This is common to all 2-wire EEPROM devices. The 32K/64K uses the three device address bits A2, A1, A0 to allow as many as eight devices on the same bus. These bits must compare to their corresponding hardwired input pins. The A2, A1, and A0 pins use an internal proprietary circuit that biases them to a logic low condition if the pins are allowed to float. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a zero. If a compare is not made, the device will return to standby state. NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. A low-V CC detector (5-volt option) resets the device to prevent data corruption in a noisy environment. DATA SECURITY: The AT24C32/64 has a hardware data protection scheme that allows the user to write protect the upper quadrant (8/16K bits) of memory when the WP pin is at VCC. The data word address lower 5 bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero, allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page, to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 4). RANDOM READ: A random read requires a "dummy" byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 5). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an 7 Write Operations BYTE WRITE: A write operation requires two 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (refer to Figure 2). PAGE WRITE: The 32K/64K EEPROM is capable of 32byte page writes. A page write is initiated the same way as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 3). acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will "roll over" and the sequential read will conFigure 1. Device Address tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 6). Figure 2. Byte Write Figure 3. Page Write Notes: 1. 2. * = DON'T CARE bits = DON'T CARE bits for the 32K 8 AT24C32/64 AT24C32/64 Figure 4. Current Address Read Figure 5. Random Read Note: 1. * = DON'T CARE bits Figure 6. Sequential Read 9 AT24C32 Ordering Information tWR (max) (ms) 10 ICC (max) (A) 3000 ISB (max) (A) 35 fMAX (kHz) 400 Ordering Code AT24C32-10PC AT24C32N-10SC AT24C32W-10SC AT24C32-10PI AT24C32N-10SI AT24C32W-10SI AT24C32-10PC-2.7 AT24C32N-10SC-2.7 AT24C32W-10SC-2.7 AT24C32-10PI-2.7 AT24C32N-10SI-2.7 AT24C32W-10SI-2.7 AT24C32-10PC-2.5 AT24C32N-10SC-2.5 AT24C32W-10SC-2.5 AT24C32-10PI-2.5 AT24C32N-10SI-2.5 AT24C32W-10SI-2.5 AT24C32-10PC-1.8 AT24C32N-10SC-1.8 AT24C32W-10SC-1.8 AT24C32-10PI-1.8 AT24C32N-10SI-1.8 AT24C32W-10SI-1.8 Package 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 8P3 8S1 8S2 Operation Range Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) Commercial (0C to 70C) Industrial (-40C to 85C) 3000 35 400 10 1500 0.5 100 1500 0.5 100 10 1000 0.5 100 1000 0.5 100 10 800 0.1 100 800 0.1 100 Package Type 8P3 8S1 8S2 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Options Blank -2.7 -2.5 -1.8 Standard Operation (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (2.5V to 5.5V) Low Voltage (1.8V to 5.5V) 10 AT24C32/64 AT24C32/64 AT24C64 Ordering Information tWR (max) (ms) 10 ICC (max) (A) 3000 ISB (max) (A) 35 fMAX (kHz) 400 Ordering Code AT24C64-10PC AT24C64N-10SC AT24C64W-10SC AT24C64-10TC AT24C64-10PI AT24C64N-10SI AT24C64W-10SI AT24C64-10TI AT24C64-10PC-2.7 AT24C64N-10SC-2.7 AT24C64W-10SC-2.7 AT24C64-10TC-2.7 AT24C64-10PI-2.7 AT24C64N-10SI-2.7 AT24C64W-10SI-2.7 AT24C64-10TI-2.7 AT24C64-10PC-2.5 AT24C64N-10SC-2.5 AT24C64W-10SC-2.5 AT24C64-10TC-2.5 AT24C64-10PI-2.5 AT24C64N-10SI-2.5 AT24C64W-10SI-2.5 AT24C64-10TI-2.5 AT24C64-10PC-1.8 AT24C64N-10SC-1.8 AT24C64W-10SC-1.8 AT24C64-10TC-1.8 AT24C64-10PI-1.8 AT24C64N-10SI-1.8 AT24C64W-10SI-1.8 AT24C64-10TI-1.8 Package 8P3 8S1 8S2 8T 8P3 8S1 8S2 8T 8P3 8S1 8S2 8T 8P3 8S1 8S2 8T 8P3 8S1 8S2 8T 8P3 8S1 8S2 8T 8P3 8S1 8S2 8T 8P3 8S1 8S2 8T Operation Range Commercial (0C to 70C) 3000 35 400 Industrial (-40C to 85C) 10 1500 0.5 100 Commercial (0C to 70C) 1500 0.5 100 Industrial (-40C to 85C) 10 1000 0.5 100 Commercial (0C to 70C) 1000 0.5 100 Industrial (-40C to 85C) 10 800 0.1 100 Commercial (0C to 70C) 800 0.1 100 Industrial (-40C to 85C) Package Type 8P3 8S1 8S2 8T 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) 8-Lead, 0.170" Wide, Plastic Gull Wing Small Outline (TSSOP) Options Blank -2.7 -2.5 -1.8 Standard Operation (4.5V to 5.5V) Low Voltage (2.7V to 5.5V) Low Voltage (2.5V to 5.5V) Low Voltage (1.8V to 5.5V) 11 Packaging Information 8P3, 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA .400 (10.16) .355 (9.02) PIN 1 .280 (7.11) .240 (6.10) .037 (.940) .027 (.690) 8S1, 8-Lead, 0150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimensions in Inches and (Millimeters) .020 (.508) .013 (.330) PIN 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .300 (7.62) REF .050 (1.27) BSC .100 (2.54) BSC .210 (5.33) MAX SEATING PLANE .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .196 (4.98) .189 (4.80) .015 (.380) MIN .022 (.559) .014 (.356) .068 (1.73) .053 (1.35) .010 (.254) .004 (.102) 0 REF 8 .050 (1.27) .016 (.406) .010 (.254) .007 (.203) .325 (8.26) .300 (7.62) .012 (.305) .008 (.203) 0 REF 15 .430 (10.9) MAX 8S2, 8-Lead, 0.200" Wide, Plastic Gull Wing Small Outline (EIAJ SOIC) Dimensions in Inches and (Millimeters) 8T, 8-Lead, Plastic Thin Small Outline Package (TSSOP) Dimensions in Millimeters and (Inches)* .020 (.508) .012 (.305) PIN 1 6.50 (.256) 6.25 (.246) PIN 1 .213 (5.41) .205 (5.21) .330 (8.38) .300 (7.62) .050 (1.27) BSC 0.30 (.012) 0.19 (.008) .212 (5.38) .203 (5.16) .080 (2.03) .070 (1.78) 1.05 (.041) 0.80 (.033) 3.10 (.122) 2.90 (.114) 1.20 (.047) MAX .65 (.026) BSC 0.15 (.006) 0.05 (.002) .013 (.330) .004 (.102) 0 REF 8 .035 (.889) .020 (.508) .010 (.254) .007 (.178) 0 REF 8 4.5 (.177) 4.3 (.169) 0.20 (.008) 0.09 (.004) 0.75 (.030) 0.45 (.018) *Controlling dimension: millimeters 12 AT24C32/64 Atmel Headquarters Corporate Headquarters 2325 Orchard Parkway San Jose, CA 95131 TEL (408) 441-0311 FAX (408) 487-2600 Atmel Operations Atmel Colorado Springs 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TEL (719) 576-3300 FAX (719) 540-1759 Europe Atmel SarL Route des Arsenaux 41 Casa Postale 80 CH-1705 Fribourg Switzerland TEL (41) 26-426-5555 FAX (41) 26-426-5500 Atmel Rousset Zone Industrielle 13106 Rousset Cedex France TEL (33) 4-4253-6000 FAX (33) 4-4253-6001 Atmel Smart Card ICs Scottish Enterprise Technology Park East Kilbride, Scotland G75 0QR TEL (44) 1355-357-000 FAX (44) 1355-242-743 Asia Atmel Asia, Ltd. Room 1219 Chinachem Golden Plaza 77 Mody Road Tsimhatsui East Kowloon Hong Kong TEL (852) 2721-9778 FAX (852) 2722-1369 Atmel Grenoble Avenue de Rochepleine BP 123 38521 Saint-Egreve Cedex France TEL (33) 4-7658-3000 FAX (33) 4-7658-3480 Japan Atmel Japan K.K. 9F, Tonetsu Shinkawa Bldg. 1-24-8 Shinkawa Chuo-ku, Tokyo 104-0033 Japan TEL (81) 3-3523-3551 FAX (81) 3-3523-7581 Fax-on-Demand North America: 1-(800) 292-8635 International: 1-(408) 441-0732 literature@atmel.com Web Site http://www.atmel.com BBS 1-(408) 436-4309 (c) Atmel Corporation 2001. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel Corporation. Other terms and product names may be the trademark of others. Printed on recycled paper. 0336G-04/01/xM |
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